Analog arithmetic circuit that can perform multiplication division expansion and compression by using delta sigma modulator

ABSTRACT

An analog arithmetic circuit for executing multiplications, divisions, compressions, expansions and combinations thereof. The arithmetic circuit is provided with a ΔΣ modulator comprising an A/D converter and a first D/A converter, a second D/A converter for receiving the output from the ΔΣ modulator, and a low-pass filter which receives the output of the second D/A converter and outputs the result of an arithmetic operation. The arithmetic circuit can be fabricated in the form of a MOS LSI because it does not use a precise triangle waveform generator for pulse width modulation.

TECHNICAL FIELD

The present invention relates to an analog arithmetic circuit, and moreparticularly to an analog arithmetic circuit adapted to executearithmetic operations such as multiplications, additions, divisions,compressions and expansions, as well as combinations thereof.

BACKGROUND ART

In some conventional analog multipliers, a multiplication is executed,for instance, by adding logarithmic functions represented by theequation I≈Is·e^(KV) that expresses the relationship between the currentI and the voltage V at a PN junction (where I=the current flowingthrough the PN junction; Is=a saturation current; V=a voltage across thePN junction; and K=a constant).

However, the voltage V across the PN junction in the conduction state ison the order of about 0.6 V, and hence, the magnitude of an analog inputsignal is limited. As a result, it has been impossible to execute amultiplication of analog signals each having a large amplitude.Furthermore, in this type of multiplication, the arithmetic operationsare frequently adversely affected by noises so that it cannot beexpected to obtain a product with a high degree of accuracy. Inaddition, it has been difficult to construct this type of analog circuitin the form of an MOS-LSI.

There has been proposed and demonstrated a time-division type multiplier(for instance, as disclosed in the Japanese Patent Application LayingOpen No. 55-82375), in which a first input voltage Ex and its invertedvoltage -Ex are alternately switched on, and the duty ratio of theswitching is subjected to the pulse-width modulation by a second inputvoltage Ey. After that, the pulse-width modulated outputs are averaged,thereby obtaining the output Ex×Ey.

In this circuit, however, the pulse-width modulated output is obtainedas a level ratio between an analog input signal Ey and a trianglewaveform signal. Consequently, the pulse duration of the output takes anarbitrary value as long as the analog input signal takes an arbitraryvalue, even if the frequency of the triangle waveform signal ismaintained constant. In other words, the pulse duration takes acontinuous value. In view of the fact that the duty ratio of thepulse-width modulation circuit varies continuously, a high-speed andhigh-accuracy analog circuit is required in order to make the duty ratiocorrectly follow the original signal.

In addition, a triangle generator in a pulse-width modulation circuitmust have a high degree of accuracy because the amplitude and frequencyof the triangle waveform signal considerably affect the modulationcharacteristics. This not only makes it difficult to fabricate thegenerator in the form of an MOS-LSI, but also makes the generatorsusceptible to noises.

Two types of conventional analog dividers are well known in the art: oneis a system utilizing a logarithmic amplifier; and the other is amultiplication-feedback system in which analog multiplier is insertedinto the feedback loop of an operational amplifier. However, the formersystem has the problems that the arithmetic operation speed is slow, andthat only the arithmetic operation can be achieved between an operatedsignal (a signal that represents the entity such as dividend) and anoperating signal (a signal that represents the entity such as divisor)of either positive or negative signs. In the case of the latter, sincethe system has the feedback loop including the multiplier, it tends tooscillate so that a satisfactory degree of stability cannot be achieved.

Two types of conventional analog expansion and compression circuits arewell known in the art: a system using a gain control circuit utilizing anonlinear characteristic of bipolar transistors; and a system using adiode-clamp piecewise linear approximation circuit including aresistor-diode network. In these systems, when they are used as anexpansion circuit, the nonlinear element is connected to the input of anamplifier, whereas when they are used as a compression circuit, thenonlinear element is inserted into the feedback loop.

As a result, the system using the nonlinear characteristic of thebipolar transistors presents the problems that each transistor has adifferent nonlinear characteristic, and that it is difficult to make thesystem compact in the form of an LSI. On the other hand, the systemusing the diode-clamp piecewise linear approximation circuit must use alarge number of resistors, and hence, it is substantially difficult toconstruct the system in the form of an LSI.

The above-described various conventional analog arithmetic circuits havetheir own defects. In addition, their circuit configurations are greatlydifferent from one another according to the arithmetic operationsdemanded, so that they cannot be used in common and cannot beuniversalized. As a result, even if it is possible to construct them inthe form of an LSI, various types of LSIs must be fabricated. This willgreatly reduce the merits resulting from the mass production system.

DISCLOSURE OF THE INVENTION

One of the objects of the present invention is to provide an analogarithmetic circuit which can substantially solve the above and otherproblems encountered in the conventional analog arithmetic circuits.

Another object of the present invention is to provide an analogarithmetic circuit which has a simple construction and a stableoperation.

A further object of the present invention is to provide an analogarithmetic circuit which can be fabricated in the form of an MOS-LSI sothat the analog arithmetic circuit can be made compact in size.

A still further object of the present invention is to provide auniversal type analog arithmetic circuit which can use a fundamentalcommon circuit for executing various arithmetic operations.

To accomplish the above objects, an analog arithmetic circuit accordingto the present invention is provided with the following elements:

a ΔΣ modulation means having an A/D conversion means which samples anoperated signal by a predetermined sampling frequency thereby outputtinga digital signal, and having a first D/A conversion means which receivesthe digital signal, outputs a first analog signal that takes a positiveor negative amplitude in response to a first reference signal, and feedsthe first analog signal back to the A/D conversion means as a differenceinput;

a second conversion mean for receiving the digital signal and outputtinga second analog signal swinging to positive and negative in response toa second reference signal; and

a low-pass filtering means for receiving the second analog signal andoutputting an analog signal representing the result of an arithmeticoperation, wherein at least one of the first reference signal or thesecond reference signal is selected as the operating signal.

The digital signal outputted from ΔΣ modulation means can be a 1-bitdigital signal.

Furthermore, each of the first and second conversion means can beconstructed with an operational amplifier and switched-capacitors.

The low pass filtering means can also be constructed with an operationalamplifier and switched-capacitors.

More preferably, the second reference signal is inputted as an operationsignal so that the output signal representative of the product of theoperated signal and the operating signal can be produced.

When the first reference signal is inputted as an operating signal, thesignal representative of the quotient obtained by dividing the operatedsignal by the operating signal can be produced.

When the signal obtained by rectifying-and-averaging operation of theoperated signal is used as the second reference signal, i.e., as anoperating signal, it becomes possible to output an expanded signal.

Furthermore, when the signal obtained by rectifying-and-averaging thequotient signal is used as the first reference signal, i.e., as theoperating single, it becomes possible to output a compressed signal.

It is preferable that the rectifying-and-averaging operation be carriedout by using switched-capacitors, a comparator, and an operationalamplifier.

More preferably, the analog arithmetic circuit can be provided with aselection means for selecting a predetermined output as the operatingsignal instead of the rectified-and-averaged output when therectified-and-averaged output is decreased below a predetermined value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a basic construction of an analogarithmetic circuit in accordance with the present invention;

FIGS. 2A-2K are diagrams illustrating waveforms at various points of theanalog arithmetic circuit of the present invention;

FIG. 3 is a block diagram illustrating a first or a second D/A converterof the analog arithmetic circuit of the present invention;

FIG. 4A is a block diagram illustrating ΔΣ modulator of the analogarithmetic circuit of the present invention;

FIG. 4B is a block diagram illustrating a circuit consisting of thesecond D/A converter and a low-pass filter of the analog arithmeticcircuit of the present invention;

FIG. 5 is a block diagram of the analog arithmetic circuit in accordancewith the present invention when it is used as a multiplier;

FIG. 6 is a block diagram of the analog arithmetic circuit in accordancewith the present invention when it is used as a divider;

FIG. 7 is a block diagram of the analog arithmetic circuit in accordancewith the present invention when it is used as an expansion circuit;

FIG. 8 is a block diagram of the analog arithmetic circuit in accordancewith the present invention when it is used as a compression circuit;

FIG. 9 is a schematic block diagram illustrating one example of anrectifying-and-averaging circuit used in the analog arithmetic circuitin accordance with the present invention;

FIG. 10 is a block diagram illustrating a more practical construction ofthe rectifying-and-averaging circuit shown in FIG. 9;

FIGS. 11A-11D are diagrams illustrating the signal waveforms at variouspoints in FIG. 7; and

FIG. 12 is a block diagram illustrating one example of a compressioncircuit wherein a minimum-output-setting unit is added to thecompression circuit shown in FIG. 8.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram illustrating the basic construction of ananalog arithmetic circuit in accordance with the present invention. Theanalog arithmetic circuit comprises ΔΣ modulator 10, a second D/Aconverter 20 and a low-pass filter 30. The basic construction of the ΔΣmodulator 10 is well known, and in general, converts an analog signalinto a pulse-density modulated signal. Various types of the ΔΣ modulatorare well known in the art.

In the analog arithmetic circuit shown in FIG. 1, a dual-modulation-typeΔΣ modulator 10 is used, which comprises operational amplifiers 11 and12, adders 13 and 14, and feedback capacitors 15 and 16 connected to theoperational amplifiers 11 and 12, respectively. Because of thecapacitors 15 and 16, each operational amplifier 11 or 12 functions asan integrator. The ΔΣ modulator further comprises a comparator 17, aflip-flop 18 for receiving the output of the comparator 17 insynchronism with clock pulses having a sampling frequency (fs), a firstD/A converter 19 (1-bit D/A converter), an input line a for inputting anoperated signal (an analog signal), a line 10b for supplying a referencesignal Vb to the first D/A converter 19, a line 10s for delivering clockpulses fs to the flip-flop 18, a line c for delivering a referenceelectrical signal Vc to the second D/A converter 20, and an output line30a of the analog arithmetic circuit.

The frequency of the clock pulses delivered through the line 10s must beat least ten times higher than the maximum frequency of the operatedsignal, and preferably should be as high as 50-1000 times. The frequencyless than 10 times is not preferable because S/N ratio declinesaccordingly.

Quantizing noise in the ΔΣ modulator 10 increases at the high frequencyband. In order to improve the frequency characteristics with regard tothe quantizing noise, the following techniques can be used: a pluralityof integrators, each using an operational amplifier, are connected in aserial fashion as shown, for instance, in FIG. 1; and/or the D/Aconverter 19 is constructed so as to convert not a single bit butmulti-bits.

Referring to FIG. 1, the operated signal (analog signal) having, forexample, a sinusoidal waveform with a peak A as shown in FIG. 2A istransmitted through the line 10a.

The operated signal (FIG. 2A) and the output from the first D/Aconverter 19 are fed to the adder 13 which in turn delivers its outputto the inverting input terminal of the operational amplifier 11. Theadder 14, receiving the output of the operational amplifier 11 and theoutput of the D/A converter 19, produces the sum of these signals, andfeeds it to the inverting input terminal of the operational amplifier12. The noninverting input terminals of the operational amplifiers 11and 12 are connected to an analog ground voltage.

The comparator 17 compares the output of the operational amplifier 12with the analog ground voltage, and outputs "1" when the output of theoperational amplifier 12 is higher than the analog ground voltage.Otherwise, it outputs "0".

The 2-value output of the comparator 17, i.e., a "1" or a "0", isdelivered to a data input terminal of the flip-flop 18. The clockpulses, the frequency fs of which is more than several tens of timeshigher than that of the operated signal Va are supplied through the line10s. In synchronism with each clock pulse, the data "0" or "1" from thecomparator 17 is read into the flip-flop 18.

Thus, the operated signal Va (FIG. 2A) is sampled at a high speed insynchronism with the clock pulse fs, and is converted, for instance,into 1-bit digital output, Vd as shown in FIG. 2B.

The comparator 17 and the flip-flop 18 are not restricted to a 1-bitcircuit. It can be multi-bit circuit. However, in the later description,the 1-bit A/D conversion will be explained for easier understanding ofthe present invention.

The digital signal Vd (FIG. 2B) forms a pulse train having pulse densityproportional to the instantaneous value of each sampling of the operatedsignal (FIG. 2A). The pulse of the digital output Vd takes only discreteduration of 1/fs (second) multiplied by an integer, because theflip-flop 18 operates in response to the clock pulse fs. Moreparticularly, as best shown in FIG. 2B, the pulse density varies inresponse to the amplitude and polarity of the operated signal Va (FIG.2A): the density of "1" increases as the input signal increases towardpositive; the density of "1" and "0" are equal when the amplitude iszero, i.e., when no signal exists.

The first D/A converter 19 converts the first reference signal into thepositive or negative analog signal ±Vb in response to the digital signalsupplied from the flip-flop 18, and the analog output thus obtained isfedback as a difference signal ±Vb to the operational amplifiers 11 and12 through the adders 13 and 14, respectively. As a result, thedifference between the current operated signal Va and the analog signal±Vb corresponding to the digital signal at the previous sampling time isalways integrated.

When the reference signal to the first D/A converter 19 is Vb, therespective difference outputs fed from the adders 13 and 14 to theoperational amplifiers 11 and 12 take the following values: when theoutput of the flip-flop 18 is "1", the difference outputs take a valueVa-Vb; whereas, when the output of the flip-flop 18 is "0", thedifference outputs take a value of Va+Vb. For instance, as shown in FIG.2C, when the reference signal Vb (=V1 or V2) applied to the first D/Aconverter 19 through the line 10b, shown in FIG. 1, the output Vd fromΔΣ modulator 10 becomes a 1-bit digital signal as shown in FIG. 2D. Whenthe reference signal Vb=V1, the digital signal (in the left half of FIG.2D) forms a pulse train with the pulse density proportional to Va inresponse to the values of the operated signal Va (FIG. 2A) and thereference signal Vb=V1. Likely, the reference signal Vb=V2, the digitalsignal becomes a pulse train with the pulse density proportional toVa/V2.

So far the reference signal Vb has been described as the positive signal(voltage or current). With regard to the negative reference signal, thepulse train can be obtained in a manner substantially similar to thatdescribed above.

When the reference signal Vb of a constant value is supplied to thefirst D/A converter 19, the output signal Vd of the ΔΣ modulator 10forms a pulse train having a pulse density proportional to the operatedsignal.

The output Vd from ΔΣ modulator 10 is delivered to the second D/Aconverter 20. For the simplicity of the explanation, the operated signalVa inputted to the line 10a is supposed to take values V₁, 0, and -V₂ asshown in FIG. 2E, and the reference signal fed through the line 10b issupposed to be maintained at a constant value. Then, the ΔΣ modulator 10will produce a pulse train shown in FIG. 2F.

Next, consider the case when the sinusoidal signal with a peak value Aas shown in FIG. 2G is delivered to the second D/A converter 20 throughthe line 20c as a reference signal Vc. In response to the "1" or "0" ofthe digital signal Vd shown in FIG. 2F, the second D/A converter 20produces the signal Ve shown in FIG. 2H, which is obtained by convertingthe signal Vc in FIG. 2G into the signal alternately swinging inpositive and negative directions.

The operation of the second D/A convertr 20 is similar to that of thefirst D/A converter 19, and hence, when the reference signal Vc theretois maintained constant, the digital output Vd of the ΔΣ modulator 10 isconverted into an analog signal directly corresponding to the digitaloutput Vd by the second D/A converter 20. The output Ve of the secondD/A converter 20 is delivered to the low-pass filter 30 so that thehigher frequency components above the cutoff frequency is suppressed. Asthe low-pass filter 30, for instance, a conventional passive filterconsisting of capacitors and resistors, or an active filter consistingof capacitors, resistors and an operational amplifier can be used.

Furthermore, the low-pass filter 30 can be constructed withswitched-capacitors. In this case, the aliasing noise problem arises,but the analog arithmetic circuit in accordance with the presentinvention has an advantage that such problem will never arise.

More specifically, the switched-capacitor filter samples the inputsignal by the sampling clock so that the signal in the frequency bandbetween (the frequency of the sampling clock multiplied by aninteger)±(the frequency of the passband of the filter) are folded backto the passband. In the conventional analog multiplier using aconventional pulse-width modulation circuit, the duration of the outputpulses is indefinite as described above, and hence, the frequencyspectrum of the output pulses will be spread over the entire band, andthe frequency spectrum of the entire band can be folded back. Therefore,in order to prevent such folding back (aliasing noise), an antialiasingfilter must be placed at the preceding stage of the switched-capacitorfilter, thus suppressing the higher frequency components above thecutoff frequency of the filter.

In contrast, according to the embodiment of the present invention, boththe sampling clock frequency fs of the ΔΣ modulator 10 and the samplingclock frequency of the switched-capacitors in the low-pass filter 30 areset sufficiently high, i.e., are selected N (an integer more then ten)times higher than the frequencies of the passband. As a result, it isnot necessary to place the antialiasing filter at the preceding stage ofthe switched-capacitor filter.

Furthermore, both the first D/A converter 19 and the second D/Aconverter 20 can be constructed by using the switched-capacitors.

FIG. 3 illustrates the first D/A converter 19 arranged by using theswitched-capacitor system (the second D/A converter 20 can be arrangedin a similar manner). The first D/A converter 19 comprises a firstswitched-capacitor circuit 21, a second switched-capacitor circuit 22,and a first gate 23 and a second gate 24 connected to the outputs of thecircuits 21 and 22, respectively. A reference signal Vb is fed throughthe line 10b, and the analog output ±Vb is produced through an outputline 25.

The first switched-capacitor circuit 21 comprises a capacitor C2, a pairof switches φ1 for discharging the capacitor C2, and another pair ofswitches φ2. The first and second switch pairs φ1 and φ2 are turned onand off by clocks that do not overlap each other.

The second switched-capacitor circuit 22 comprises a capacitor C3, and afirst and a second switch pairs φ1 and φ2 for charging and dischargingthe capacitors C3, which are arranged in a manner different from theswitch pairs φ1 and φ2 described above.

Next, the operation of the first D/A converter 19 will be described inmore detail.

When the switches φ1 are turned on and the switches φ2 are turned off,the capacitor C2 is discharged, while the capacitor C3 is charged. Incontrast, when the switches φ1 are turned off and the switches φ2 areturned on, the capacitor C2 is ready to be charged, while the capacitorC3 is ready to be discharged. Assuming that the flip-flop 18 in FIG. 1in the ΔΣ modulator 10 outputs a 1-bit digital signal, either the firstgate 23 or the second gate 24 is selected in response to the output Q orQ.

When the output Q is fed, the first gate 23 is turned on so that thereference voltage, Vb charging the capacitor C2, is supplied to the nextstage via the output line 25. On the other hand, when the output Q isfed, the second gate 24 is turned on, and the stored charge in thecapacitor C3 opposite in voltage to the reference signal Vb is outputtedthrough the output line 25.

Thus, the referece signal Vb supplied through the line 10b is convertedinto a positive or a negative analog signal of a constant magnitude, ±Vband is outputted through the output line 25 in response to the digitalsignal Q or Q.

FIG. 4A illustrates the ΔΣ modulator 100 using the D/A converter 19described above with reference to FIG. 3.

The ΔΣ modulator 100 comprises a first sampling unit 106 for samplingthe operated signal, operational amplifiers 102 and 103, feedbackcapacitors C4 and C6 connected to the operational amplifiers 102 and103, respectively, a comparator 104, a D flip-flop 105, a first D/Aconverter 19, a second sampling unit 107, and an adder 108. Theoperation of the switches φ1 and φ2, and the output signals Q and Q aresubstantially similar to those described above with reference to FIG. 3.

The operated signal Va supplied through the line 10a charges thecapacitor C1 so as to be sampled while the switches φ1 in the firstsampling unit 106 are turned on. In contrast, when the switches φ2 areturned on, the charged (sampled) signal is supplied through an addingpoint 109 to the operational amplifier 102 in which the operated signalVa is integrated. The output of the operational amplifier 102 chargesthe capacitor C5 so as to be sampled in the second sampling unit 107when the switches φ1 are turned on. Then, the charged (sampled) signalis supplied to the operational amplifier 103 so as to be integrated whenthe switches φ2 are turned on.

When the switches φ2 is turned on, the capacitor C7 is charged by theoutput from the operational amplifier 103, and the capacitor C8 ischarged by the output from the operational amplifier 102. Both theoutputs of these capacitors are added by the adder 108, and aredelivered to the comparator 104 so as to be compared with the groundvoltage. In response to the result of comparison, the comparator 104delivers the output "1" or "0" to the flip-flop 105.

This output, which is latched into the flip-flop 105 by the leading edgeof the clock pulse having the sampling frequency fs, is produced as a1-bit digital signal Q and Q.

FIG. 4B illustrates a circuit constructed into one body by integratingthe second D/A converter 20 and the low-pass filter 30 in FIG. 1 usingswitched capacitors. A second D/A converter 110 includingswitched-capacitors 111 and 112 is substantially similar in constructionto the first D/A converter 19 described above with reference to FIG. 3.The output from the second D/A converter 110 is delivered to theinverting input terminal of an operational amplifier 113. To thenoninverting input terminal thereof, on the other hand, the analogground voltage is applied. A capacitor C₁₁ and a switched-capacitor 114are interconnected between the inverting input terminal and the outputline 113a of the operational amplifier 113.

In response to the output Q or Q from the ΔΣ modulator 10, the secondD/A converter 110 supplies the reference signal Vc entering the line 20cto the noninverting input terminal of the operational amplifier 113,either in a noninverting form +Vc or in an inverting form Vc. Owing tothe charging and discharging of the capacitor C₁₀ in response to theON/OFF of the switches φ1 and φ2, the switched-capacitor 114 functionsas a kind of feedback resistor, and operates as a low-pass filter inconjunction with the switched-capacitor 111 or 112. In short, thereference signal Vc is not reversed or reversed in response to theoutputs Q and Q of the ΔΣ modulator 10, and the high frequency componentof the reference signal Vc is cut off by the low-pass filter, and thenthe output signal of the filter is produced from the output line 113a.

The analog arithmetic circuit in accordance with the present inventioncan execute various arithmetic operations such as multiplication,division, expansion, compression and the combinations thereof bysupplying on operated or operating signal (analog signal) as a referencesignal to at least one of the first and second D/A converters 19 and 20as will be described hereinafter.

1) Multiplication (FIG. 5)

An operated signal Va is fed to the line 10a, an operating signal Vc isfed to the line 20c, and a constant reference signal Vb is applied tothe line 10b so that the product Vo=Va×Vc can be obtained from the line30a.

2) Division (FIG. 5)

An operated signal Va is fed to the line 10a, an operating signal Vb isapplied to the line 10b, and a constant reference voltage Vc is fed tothe line 20c. Then the output Vo=Va/Vb is derived from the output line30a.

3) Expansion (FIG. 7)

An operated signal Va is fed to the line 10a; the signal obtained byprocessing the operated signal Va by the rectifying-and-averagingcircuit 40 (to be described in detail hereinafter) is applied to theline 20c as an operating signal Vc; and a predetermined constantreference voltage Vb is applied to the line 10b. Then the expandedsignal Vo of the operated signal Va A is obtained from the output line30a.

4) Compression (FIG. 8)

An operated signal Va is delivered to the line 10a; the signal Vbobtained by processing the output signal from the line 30a by therectifying-and-averaging circuit 50 (to be described in more detailhereinafter) is applied to the line 10b; and a predetermined constantreference voltage Ve is supplied to the line 20c. Then the compressionsignal Vo of the operated signal Va can be derived from the output line.

5) Multiplication and Division

An operated signal Va is applied to the line 10a; an operating signal Vbis supplied to the line 10b; and another operating signal Vc isdelivered to the line 20c. Then the result (Va×Vc)/Vb is derived fromthe output line 30a.

6) AGC (Automatic Gain Control)

An operated signal Va is delivered to the line 10a; the signal obtainedby processing the operated signal Va by the rectifying-and-averagingcircuit (to be described in detail hereinafter) is supplied to the line10b as the operating signal Vb; and a predetermined constant referencevoltage Vc is applied to the line Vc. Then, the analog signal Vo havinga constant amplitude regardless of the average level of the operatedsignal Va can be obtained from the output line 30a.

7) Combinations of the Arithmetic Operations

An operated signal Va is delivered to the line 10a; the signal Vbobtained as in 4) above is supplied to the line 10b; and an operatingsignal Vc is applied to the line 20c. Then, the compression signal Vo ofthe product (Va×Vc) can be derived from the output line 30a.Furthermore, when an operated signal Va is applied to the line 10a, thesignal Vc obtained as in 3) above is supplied to the line 20c, and anoperating signal Vb is applied to the line 10b, the output Vo which theexpansion signal of the quotient Va/Vb is derived from the output line30a.

As described above, the analog arithmetic circuit in accordance with thepresent invention can execute various arithmetic operations. If it isrequired to supply two or more operating signals to the first or secondD/A converter 19 and 20 as a reference signal, it is sufficient toprovide another adder so as to obtain the sum total of a plurality ofthe operating signals. In like manner, when it is necessary to deliver aplurality of operated signals, it is sufficient to provide an adder soas to obtain the sum total of the operated signals.

Each of the signals delivered to the lines 10a, 10b and 20c can be avoltage or current signal depending on the construction of the circuit.

Practical examples of various arithmetic operations carried out by theanalog arithmetic circuit shown in FIG. 1 will be described.

MULTIPLIER

FIG. 5 is a block diagram illustrating the fundamental construction ofthe multiplier. A predetermined constant reference signal Vb to beapplied to the first D/A converter 19 is generated within the circuit.For example, a sinusoidal operating signal Vc shown in FIG. 2G issupplied as the reference signal to the second D/A converter 20 throughthe line 20c. When the analog signal shown in FIG. 2E is delivered tothe line 10a as an operated signal Va, a pulse train Ve shown in FIG. 2Hwith the pulse density corresponding to the product and Va×Vc isproduced in response to the clock pulses fs transmitted through the line10s, and is delivered to the low-pass filter 30 which suppresses thehigh frequency component. Thus, the product output Vo(=Va×Vc) shown inFIG. 2I is derived from the output line 30a.

DIVIDER

FIG. 6 is a block diagram illustrating a basic construction of adivider. A predetermined constant reference signal Vc generated in thecircuit is applied to the second D/A converter 20, and the operatingsignal V₁ and V₂ in the form of an electric current shown in FIG. 2C aredelivered to the line 10b as a reference signal for the first D/Aconverter 19.

When a sinusoidal waveform having an amplitude A as shown in FIG. 2A isdelivered to the line 10a as an operated signal Va, the pulse train Vdwith the pulse density proportional to Va/Vb(=A/V₁ or A/V₂) as shown inFIG. 2D is delivered to the second D/A converter 20 in synchronism withthe clock pulse fs transmitted through the line 10s. The high frequencycomponent is then cut off by the low-pass filter 30, and the quotientVo(=Va/Vb) shown in FIG. 2J is obtained from the output line 30a.

EXPANSION CIRCUIT

FIG. 7 is a block diagram illustrating a fundamental construction of anexpansion circuit. The operated signal Va transmitted through the line10a is processed by the rectifying-and-averaging circuit 40 and isdelivered through the line 20c to the second D/A converter 20 as thereference signal Vc. On the other hand, a predetermined constant signalVb is generated in the first D/A converter 19, and is applied thereto.The second D/A converter 20, in response to the digital signal Vd fromthe flip-flop 18, converts the reference signal Vc into a pulse trainwith positive and negative pulses representing the polarity and thedensity of the reference signal Vc. After that, the output signal Vc ofthe second D/A converter 20 is filtered by the low-pass filter 30, andthe expanded signal Va of the operated signal is produced from theoutput line 30a.

FIG. 9 is a block diagram illustrating a basic construction of arectifying-and-averaging circuit 40 which comprises a rectifier 201, andan averaging circuit 202 connected to the output terminal of therectifier 201. As the rectifier 201, a full-wave or half-wave rectifierutilizing diodes can be used. The averaging circuit 202 is a kind oflow-pass filter, and for instance, as shown in FIG. 9, is constructed byan operational amplifier 205 with a feedback loop consisting of acapacitor C₁₃ and a resistor connected in parallel each other.

FIG. 10 illustrates the rectifying-and-averaging circuit 40 which isconstructed with switched-capacitors. The construction shown in FIG. 10uses the outputs from a comparator 203 and an inverter 204 as gatesignals instead of using the output Q and Q from ΔΣ modulator 10 whichare used as gate signals of the switched-capacitors in FIG. 4B: therectifying-and-averaging circuit 40 compares the input signal suppliedto the input line 40d with the ground voltage by the comparator 203, andproduces the gate signals.

When the input signal supplied to the input line 40d is positive, theinput signal is delivered through a switched-capacitor 207 and a gate to211 an operational amplifier 205 which transmits and outputs only thelow frequency component using a switched-capacitor 208 and a capacitorC₁₇.

On the other hand, when the input signal is negative, the output fromthe comparator 203 is inverted through an inverter 204, and the outputgate 211 of the switched-capacitor 206 is turned on. The input signaltransmitted through the input line 40d is inverted by usingswitched-capacitors 206 and 208, the capacitor C₁₇, and the operationalamplifier 205, and only the low frequency component is outputted.

As described above, the rectifying-and-averaging circuit 40 functions asa rectifying circuit: when the signal entering the input line 40d ispositive, it is maintained positive, whereas when the signal isnegative, it is reversed to positive. In such a way, therectifying-and-averaging circuit 40 accomplishes the rectification, andin addition, delivers the low frequency component, thereby accomplishingthe averaging operation. Incidentially, the cutoff frequency of thelow-pass filter is preferably lower than that of the low-pass filtershown in FIG. 4B.

Referring back to FIG. 7, when an analog signal with the maximumamplitude X shown in FIG. 11A is delivered to the line a as an operatedsignal, Va the output Vd from the ΔΣ modulator 10 takes a form of apulse train with the pulse density proportional operated to the analogsignal Va of FIG. 11A as shown in FIG. 11B.

The operated signal Va with the maximum amplitude X shown in FIG. 11A isalso delivered to the rectifying-and-averaging circuit 40 so that theanalog signal output Vc with the amplitude α (not shown) can be derived.

The output Ve of the second D/A converter 20 takes a pulse-shapedwaveform shown in FIG. 11C, the pulse density of which is proportionalto the amplitude of the operated signal Va with the maximum amplitude X,and the amplitude of which is equal to the amplitude α of the output Vcfrom the rectifying-and-averaging circuit 40.

The output Ve thus obtained is transmitted through the low-pass filter30. As a result, the output signal shown in FIG. 11D, the wave shape ofwhich is substantially similar to that of the operated signal, Va inFIG. 11A and the amplitude of which is X, is obtained from the low-passfilter 30.

Next, when the operated signal Va with the maximum amplitude Y (see FIG.11A) is delivered to the input line Va, the amplitude of the output Vofrom the rectifying-and-averaging circuit 40 takes a value β, and theabove-mentioned values X, Y, α and β have the following relation:

    Y/X=β/α

In addition, the pulse density of the output Vd of ΔΣ modulator 10varies to (Y/X) times the previous density. Incidentally, the pulsetrain shown in FIG. 11B is drawn as if the pulse density thereof werenot varied, but in practice, the pulse density varies.

Hence, the amplitude of the operated signal Va with the maximumamplitude Y, when it has passed through the low-pass filter 30, isincreased by the ratio expressed by the following equations:

    y/x=(β/α)·(Y/X)=(Y/X)·(Y/X)=(Y/X).sup.2 ·

This is because, in the case of the analog signal Va with the amplitudeY, the input signal Vc fed from the rectifying-and-averaging circuit 40to the second D/A converter 20 is increased by the factor β/α, and atthe same time the pulse density of the pulse train Vd fed from theflip-flop 18 to the second D/A converter 20 is increased by the factorY/X, compared with the analog signal Va with the maximum amplitude X. Asa result, the ratio between these two output signals from the low-passfilter 30 becomes a square of the ratio of the maximum amplitudes of theoriginal input signals.

So far it has been described that X and Y have their respective constantamplitudes, so that α and β are maintained constant. However, if each Xand Y represents and arbitrary amplitude of the operated signal, Va αand β have the amplitudes and pulse density in accordance with theamplitudes X and Y. Thus, the above-mentioned relation can bemaintained, and hence, the dynamic range of the input signal isexpanded, whereby the function of the expansion circuit is accomplished.

COMPRESSOR

FIG. 8 is a block diagram illustrating a basic construction of acompressor. The operated signal Va is transmitted through the input line10a. The analog output signal Vo produced from the output line 10a isfurther processed by a rectifying-and-averaging circuit 50, and isdelivered through the line 10b to the first D/A converter 19 as thereference signal Vb. The predetermined constant reference signal Vc isgenerated within the second D/A converter 20, and is supplied thereto.As the rectifying-and-averaging circuit 50, a circuit similar to thatused in the expansion circuit described above can be used.

In FIG. 8, the analog signal Va with the maximum amplitude A shown inFIG. 2A is applied to the input line 10a, and the signal with theamplitude B (to be described in detail hereinafter) is delivered to thefirst A/D converter 19 as the reference signal Vb. Then the ΔΣ modulator10 outputs a pulse train Vd with the pulse density proportional to A/Bas shown in FIG. 2D. When the signal thus obtained is transmittedthrough the second A/D converter 20 and the low-pass filter 30, thesignal with the maximum amplitude C shown in FIG. 2K is obtained.

In this case, when the signal Vo shown in FIG. 2K is transmitted throughthe rectifying-and-averaging circuit 50, the reference signal Vb withthe amplitude B is obtained.

The above-mentioned amplitude C is proportional to A/B, and in additionB is proportional to C so that the following equation is obtained:

    C=K.sub.1 ·(A/B)=K.sub.1 ·A·(1/K.sub.2 ·a)

and the above equation can be transformed into ##EQU1## Therefore, theanalog output signal Vo derived from the output line 30a is proportionalto the root of the operated signal Va entering the input line 10a. Thus,the dynamic range (represented by logarithm) of the operated signal Vacan be compressed by one half.

When the operated signal Va entering the input line 10a approaches zero,the output signal Vo derived from the output line 30a also approacheszero. As a result, the reference signal Vb applied to the first D/Aconverter 19 also approaches zero so that the stable operation cannot beensured.

To prevent this, a minimum-output-setting circuit 300 shown in FIG. 12is provided in addition to the rectifying-and-averaging circuit 50. Whenthe output of the rectifying-and-averaging circuit 50 declines below theoutput of the minimum-output-setting circuit 300, the input Vb to thefirst D/A converter 19 is switched from the output of therectifying-and-averaging circuit 50 to the output of theminimum-output-setting circuit 300 by means of a comparator 301 and aswitch 302. Thus, the above-described unstable operation can be avoided.

The minimum-output-setting circuit 300 shown in FIG. 12 will bedescribed in more detail hereinafter.

The ΔΣ modulator 10, the second D/A converter 20, the low-pass filter 30and the rectifying-and-averaging circuit 50 are arranged in a mannersubstantially similar to those described hereinbefore. The outputvoltage of the minimum-output-setting circuit 300 is determined to avoltage at which the operation of the arithmetic operation circuitbecomes unstable because of the decline of the output of therectifying-and-averaging circuit 50. In this case, the voltage set bythe circuit 300 is assumed to be, for instance, 10 mV. The comparator301 compares the output of the rectifying-and-averaging circuit 50 withthe output voltage derived from the minimum-output-setting circuit 300.When the output voltage from the rectifying-and-averaging circuit 50declines below 10 mV, in response to the signal from the comparator, theinput signal Vb applied to the input line 10b of the first D/A converter19 (FIG. 8) is switched from the output of the rectifying-and-averagingcircuit 50 to the output of the minimum-output-setting circuit 300. Whenthe output signal of the minimum-output-setting circuit 300 is deliveredto the input line 10b, the output of the analog arithmetic circuit isproportional to the operated signal, Va and its operation is stabilized.

The lower the output voltage produced from the minimum-output-settingcircuit 300, the wider the compression region, and the narrower theproportional region. This will make the operation more unstable. Incontrast, the higher output voltage of the minimum-output-settingcircuit 300 makes the operation more stable, although the compressionregion is made narrower.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, ΔΣ modulator,the D/A converters and the low-pass filter are utilized. As a referencesignal for the first and/or second D/A converters, an operating signalis applied to one or both of the converters so that various arithmeticoperations such as multiplication, division, expansion, compression andthe combinations thereof can be executed.

Furthermore, the present invention can provide an analog arithmeticcircuit which is simple in construction and can be made compact in sizein the form of an LSI. Moreover, a common circuit can provide variousarithmetic circuits so that the data associated with the circuit can becollected as a library. This makes it possible to shorten the time fordesigning the analog arithmetic circuit, and in addition, to systematizethe design in conjunction with other circuits.

We claim:
 1. An analog arithmetic circuit which receives an operated signal and a variable operating signal, and outputs the result of an arithmetic operation, said analog arithmetic circuit comprising;ΔΣ modulation means having A/D conversion means and first D/A conversion means, said A/D conversion means sampling said operated signal at a predetermined sampling frequency, thereby outputting a digital signal, and said first D/A conversion means receiving said digital signal, and outputting a first analog signal that takes a positive or negative amplitude determined by a binary state of said digital signal and an amplitude of a first reference signal applied to said first D/A conversion means, said first D/A conversion means including means for feeding said first analog signal back to said A/D conversion means as a feedback signal to an input of said D/A conversion means to produce a difference signal between the operated signal and the feedback signal; second D/A conversion means for receiving said digital signal and outputting a second analog signal that takes a positive or negative amplitude determined by a binary state of said digital signal and an amplitude of a second reference signal applied to said second D/A conversion means; and low-pass filtering means for receiving said second analog signal and outputting an analog signal representing the result of an arithmetic operation, wherein the analog arithmetic circuit includes means for applying at least one of first reference signal and said second reference signal as said variable operating signal.
 2. An analog arithmetic circuit as claimed in claim 1, wherein the digital signal outputted from said ΔΣ modulation means is a 1-bit digital signal.
 3. An analog arithmetic circuit as claimed in claim 1, wherein each of said first and second D/A conversion means comprises a first switched-capacitor circuit, a first gate whose input is connected to an output of said first switched capacitor circuit, a second switched capacitor circuit, and a second gate whose input is connected to an output of said second switched capacitor circuit, said first or second reference signal being applied to each input of said first and second switched capacitor circuits, each output of said first and second gate being connected in common to form the output of said D/A conversion means, and each control terminal of said first and second gate being connected to said first or second D/A conversion means to receive the digital signal applied thereto.
 4. An analog arithmetic circuit as claimed in claim 1, wherein said low-pass filter comprises an operational amplifier, a switched capacitor circuit which is connected betwen an inverting input and an output of said operational amplifier, and a capacitor connected in parallel with said switched-capacitor circuit.
 5. An analog arithmetic circuit as claimed in claim 1, wherein said first reference signal has a constant amplitude, and the analog arithmetic circuit includes means for applying said second reference signal as said variable operating signal, and means for producing a signal representative of a product obtained by multiplying said operated signal and said variable operating signal.
 6. An analog arithmetic circuit as claimed in claim 5, including means for obtaining said variable operating signal by rectifying and averaging said operated signal, and means for expanding said operated signal by squaring it.
 7. An analog arithmetic circuit as claimed in claim 1, wherein said second reference signal has a constant amplitude, and the analog arithmetic circuit includes means for applying said second reference signal as said variable operating signal and means for producing a signal representative of a quotient obtained by dividing said operated signal by said variable operating signal.
 8. An analog arithmetic circuit as claimed in claim 7, including means for obtaining said variable operating signal by rectifying and averaging said quotient signal, and means for compressing said operated signal by taking a root of it.
 9. An analog arithmetic circuit as claimed in claim 7 or in claim 8, wherein the rectifying and averaging operation of said quotient signal is carried out by using switched capacitors, a comparator and an operational amplifier.
 10. An analog arithmetic circuit as claimed in claim 8, wherein the rectifying and averaging operation is carried out by a rectifying-and-averaging circuit comprising:a first switched-capacitor circuit whose input is connected to an input of said rectifying-and-averaging circuit; a first gate connected to an output of said first switched-capacitor circuit; a second switched-capacitor circuit whose input is connected to the input of said rectifying-and-averaging circuit; a second gate connected to an output of said second switched-capacitor circuit; a comparator having an input connected to the input of said rectifying-and-averaging circuit and whose output is connected to a control terminal of said second gate; an inverter whose input is connected to the output of said comparator and whose output is connected to a control terminal of said first gate; an operational amplifier whose inverting input is connected to outputs of said first and second gates; a capacitor connected between the inverting input and an output of said operational amplifier; and switched capacitor circuit connected between the output and input of said operational amplifier.
 11. An analog arithmetic circuit as claimed in claim 8, further comprising:a minimum-output-setting means for setting a predetermined minimum value; a comparator for comparing the rectified-and-averaged output with the predetermined minimum value; switching means for selecting, in response to an output of said comparator, the rectified-and-averaged output when it is greater than the predetermined minimum value, or the predetermined value when the rectifying-and-averaged value is less than the predetermined value. 